Allwinner /D1H /SMHC[2] /SMHC_CLKDIV

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Interpret as SMHC_CLKDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CCLK_DIV0 (off)CCLK_ENB 0 (on)CCLK_CTRL 0 (not_mask)MASK_DATA0

CCLK_ENB=off, CCLK_CTRL=on, MASK_DATA0=not_mask

Description

Clock Control Register

Fields

CCLK_DIV

Card Clock Divider

CCLK_ENB

Card Clock Enable

0 (off): Card Clock is off

1 (on): Card Clock is on

CCLK_CTRL

Card Clock Output Control

0 (on): Card clock is always on

1 (off_idle): Turn off card clock when FSM is in IDLE state

MASK_DATA0

0 (not_mask): Do not mask data0 when update clock

1 (mask): Mask data0 when update clock

Links

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